1. Field of the Invention
The present invention relates to a semiconductor device having a special interconnection insulating structure and also to a method of manufacturing the semiconductor device.
2. Description of the Related Art
Improvement of an LSI (Large Scale Integrated Circuit) essentially resides in an increase in the density at which elements are packed in the LSI, namely in a decrease in the size of the elements. If the packing density of elements is increased, however, the inter-wire capacitance will increase. The greater the inter-wire capacitance, the more difficult it will be to enhance the performance of the LSI (e.g., the operating speed).
To enhance the performance of an ultra-large scale integrated circuit (ULSIC) such as a microprocessor, it is absolutely necessary to reduce the parasitic resistance and parasitic capacitance of the wires used in the ULSIC. The parasitic resistance of the wires can be decreased by using a low-resistivity material for the wires. At present, it is proposed that the wires be made of copper, instead of aluminum alloy. This is because the resistivity of copper is 30% or more lower than that of aluminum alloy.
The parasitic capacitance of the wires has two components. The first component is the capacitance among wires located at different levels. This capacitance can be reduced by increasing the thickness of the inter-layer insulating films used. The second component is the capacitance among wires located at the same level. This capacitance can be reduced by increasing the space between the wires and by decreasing the thickness of the wires.
To increase the space between the wires is to lower the packing density of elements, and to decrease the thickness of the wires is to increase the resistance of the wires. Hence, if the wires are spaced farther apart and made thicker, the performance of the LSI can no longer be enhanced. In order to reduce the parasitic capacitance among the wires, it is proposed that the insulating layers interposed between the wires be made of material having a small dielectric constant .epsilon..
FIG. 233 shows a semiconductor device in which insulating layers having a small dielectric constant are interposed between the wires. AS shown in FIG. 233, an insulating layer 12 is provided on a semiconductor substrate 11. Lines 13 are formed on the insulating layer 12. Formed on the layer 12 and on the wires 13 is a plasma TEOS layer 14 which contains fluorine. The plasma TEOS layer 14 containing fluorine has a dielectric constant .epsilon. of about 3.3, which is about 15% less than the dielectric constant of plasma TEOS which does not contain fluorine.
As the packing density of elements has been increasing steadily, the performance of LSIs cannot be enhanced unless the inter-wire insulating layers have a dielectric constant .epsilon. of less than 3.3. Thus, the dielectric constant of inter-wire insulating layers must be decreased by any means to improve the performance of LSIs. It is, however, extremely difficult to reduce the constant to a value less than 3.3. The inter-wire insulating layers used at present, which has a dielectric constant of 3.3 or more, is a bar to the improvement of LSIs in terms of their performance.
In recent years, an attempt has been made to void the spaces between the wires arranged at the same level so as to reduce the parasitic capacitance among these wires. This technique is disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication 7-45701. More specifically, water is filled in the inter-wire spaces, cooled to solidify, turning into ice layers, and the ice layers are evaporated, rendering the spaces void.
This technique is disadvantageous in three respects because a change in phase of the material is utilized. First, the water filled in the inter-wire spaces adversely influences the wires as it solidifies and expands. This holds true of any other material that is disclosed in the above-identified publication and that can be used in place of water. Second, the ice layers in the inter-wire spaces may melt away in some cases, due to the heat generated as they are polished by CMP (Chemical Mechanical Polishing). Third, the wafer must be cooled to a low temperature (below 0.degree. C. when water is used) until the ice layers are evaporated. This inevitably makes it difficult to handle the semiconductor wafer.
Moreover, the water vapor which fills the inter-wire spaces for some time after the ice layers have been evaporated may cause short-circuiting of the wires or corrosion of the wires, or both. The water vapor may therefore impair the reliability of the wires.
Further, this technique cannot make void the spaces between wires which are arranged at different levels. Therefore, it does not serve to reduce the parasitic capacitance among all wires, including those located at the same level, as much as is desired.